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INTEGRATED CIRCUITS
DATA SHEET
TDA9847 TV and VTR stereo/dual sound processor with digital identification
Preliminary specification Supersedes data of September 1993 File under Integrated Circuits, IC02 1995 May 23
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
FEATURES * Supply voltage 5 to 8 V * Source selector * Stereo matrix * AF inputs for external stereo AF signals (SCART or NICAM) * AF outputs for main and SCART * LED operation mode indication (stereo and dual) * High identification reliability. QUICK REFERENCE DATA SYMBOL VP IP Vi(rms) PARAMETER supply voltage (pin 22) supply current (pin 22) nominal input signal voltage Vi1 to Vi4 (RMS value) nominal output signal voltage (RMS value) clipping level of the output signal voltages (RMS value) without LED current 54% modulation B/G L Vo(rms) Vo(rms) 54% modulation THD 1.5%; B/G or L VP = 5 V VP = 8 V ILon Vi pil S/N(W) THD Tamb fident tident on Vi tuner fpil input current input voltage sensitivity of pilot frequency weighted signal-to-noise ratio total harmonic distortion operating ambient temperature identification window width total identification time on identification voltage sensitivity pull-in frequency range of pilot PLL fosc = 10.008 MHz lower side upper side ORDERING INFORMATION TYPE NUMBER TDA9847 TDA9847T 1995 May 23 PACKAGE NAME SDIP24 SO24 DESCRIPTION plastic shrink dual in-line package; 24 leads (400 mil) plastic small outline package; 24 leads; body width 7.5 mm 2 -296 302 - - stereo dual LED on unmodulated 1.4 2.4 - 5 66 - 0 2.2 2.3 0.35 - 1.60 2.65 - - 75 0.2 - - - - 28 - - - 250 500 500 CONDITIONS MIN. 4.5 14 TYP. 5 15 GENERAL DESCRIPTION
TDA9847
The TDA9847 is a stereo/dual sound processor for TV and VTR sets. Its identification ensures safe operation by using internal digital PLL technique with extremely small bandwidth, synchronous detection and digital integration (switching time maximum 2.0 s; identification concerning the main functions).
MAX. 8.8 20 - - -
UNIT V mA mV mV mV
- - 12 100 - 0.3 +70 2.2 2.3 2.0 - -296 302
V V mA mV dB % C Hz Hz s dBV Hz Hz
"CCIR468-3"
VERSION SOT234-1 SOT137-1
1995 May 23
CD1 10 nF 5% 6 dB (AM) 2.2 k Vi1 2.2 k L+R ,A 2 250 mV RMS (AM: 500 mV RMS) 35 k Vref 50 k Vi2 10 R, B 2.2 F 0 dB 5 k Vref L 10 k 10 k 2.2 F 17 CD2 21 9 3 dB 15 k 3 dB A/mono 3 dB 0 dB 5 k 250 mV RMS
BLOCK DIAGRAMS
Philips Semiconductors
TV and VTR stereo/dual sound processor with digital identification
250 mV RMS 10 nF 5% Vref Vref
SCART Vi4 Vi3 250 mV RMS
2.2 F 12 50 k
2.2 F 11 Vo1
6 dB 50 k AM 250 mV RMS 6 dB
500 mV RMS
14
main 500 mV RMS 13 Vo2
L/A/mono 250 mV RMS 6 dB R/B 250 mV RMS 6 dB 500 mV RMS 16
Vo3
SCART 500 mV RMS 15 Vo4
TDA9847
RFP CFP mute 30 k 47 pF 7 3.3 nF tan 0.002 CDCL Qo= 70 2.5 mH 6 100 nF Vref Vref 25 k 1 OSCILLATOR CAGC 10 F CLP 10 nF 5 23 1/2 VP 10 MHz Cref 100 F/ 16 V VP 8 22 20
MED803
3
stereo transmission 19 1 k 18 dual transmission C1 C2 C3 C4 VP
DIGITAL PLL AND DEMODULATOR
dual bit DIGITAL INTEGRATOR (274 Hz) stereo bit
DIGITAL PLL
DIGITAL PLL AND DEMODULATOR
DIGITAL INTEGRATOR (117 Hz)
4
25 k Vref SUPPLY POWER-ON RESET
CONTROL LOGIC
2 24 3
Preliminary specification
TDA9847
Input and output levels are nominal values related to the SCART norm (AM: m = 0.54, FM: f = 27 kHz).
Fig.1 Block diagram of the bipolar TV/VTR-stereo decoder.
1995 May 23
6 dB (AM) 2.2 k Vi1 2.2 k L+R ,A 2 250 mV RMS (AM: 500 mV RMS) 35 k Vref 50 k Vi2 10 R, B 2.2 F 0 dB 5 k Vref L 10 k 10 k 2.2 F 9 3 dB 15 k 3 dB A/mono 3 dB 0 dB 250 mV RMS
Philips Semiconductors
TV and VTR stereo/dual sound processor with digital identification
CD1 10 nF 5%
CD2
250 mV RMS 10 nF 5%
SCART Vi4 Vi3 250 mV RMS
2.2 F 12
17
21 Vref Vref 50 k
2.2 F 11 Vo1
6 dB 50 k AM 250 mV RMS 6 dB
500 mV RMS
14
5 k
main 500 mV RMS 13 Vo2
L/A/mono 250 mV RMS 6 dB R/B 250 mV RMS 6 dB 500 mV RMS 16
Vo3
SCART 500 mV RMS 15 Vo4
TDA9847
RFP mute 27 k 180 pF 7 1.8 nF 2% tan 0.01 CDCL 4.7 mH 5% Qo= 25 6 100 nF Vref Vref DIGITAL PLL AND DEMODULATOR dual bit DIGITAL INTEGRATOR (274 Hz) stereo bit 19 1 k 18 dual transmission 1 OSCILLATOR CAGC 10 F CLP 10 nF 5 23 1/2 VP 10 MHz Cref 100 F/ 16 V 8 22 20
MED804
stereo transmission
4
CFP DIGITAL PLL 25 k 4 25 k
VP
DIGITAL PLL AND DEMODULATOR
DIGITAL INTEGRATOR (117 Hz)
C1 C2 C3 C4
Vref
SUPPLY
POWER-ON RESET
CONTROL LOGIC
2 24 3
Preliminary specification
VP
TDA9847
Input and output levels are nominal values related to the SCART norm (AM: m = 0.54, FM: f = 27 kHz). The components of the external LC band-pass filter have the following order-No.: Philips Germany only No: 4312 020 17525 or Fastron Sdn. Bha., Malaysia type SMCC 472 J for L = 4.7 MHz (5%) Philips Components No: 2222 429 71802, C = 1.8 nF (2%).
Fig.2 Block diagram of the bipolar TV/VTR-stereo decoder with fixed coil (alignment-free).
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
PINNING SYMBOL C1 C2 C4 CAGC CLP CDCL Vi pil Cref Vi1 Vi2 Vi3 Vi4 Vo2 Vo1 Vo4 Vo3 CD1 LEDDU LEDST GND CD2 VP XTAL C3 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION control input Port C1 control input Port C2 control input Port C4 AGC capacitor of pilot frequency amplifier identification low-pass capacitor DC loop capacitor pilot frequency input voltage capacitor of reference voltage (12VP) AF input signal voltage 1 [from sound carrier 1 or AM sound (standard L)] AF input signal voltage 2 (from sound carrier 2) AF input signal voltage 3 (SCART) AF input signal voltage 4 (SCART) AF output signal voltage 2 (main) AF output signal voltage 1 (main) AF output signal voltage 4 (SCART) AF output signal voltage 3 (SCART) 50 s de-emphasis capacitor of AF Channel 1 LED (dual) LED (stereo) ground (0 V) 50 s de-emphasis capacitor of AF Channel 2 supply voltage (5 to 8 V) 10 MHz crystal input control input Port C3
C1 C2 C4 CAGC CLP CDCL Vi pil Cref Vi1 1 2 3 4 5 6
TDA9847
24 C3 23 XTAL 22 VP 21 CD2 20 GND 19 LEDST
TDA9847
7 8 9 18 LEDDU 17 CD1 16 Vo3 15 Vo4 14 Vo1 13 Vo2
MED805
Vi2 10 Vi3 11 Vi4 12
Fig.3 Pin configuration.
1995 May 23
5
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
FUNCTIONAL DESCRIPTION AF signal handling The input AF signals, derived from the two sound carriers, are processed in analog form using operational amplifiers. De-matrixing uses the technique of two amplifiers processing the AF signals. Finally, a source selector provides the facility to route the mono signal through to the outputs (`forced mono'). De-emphasis is performed by two RC low-pass filter networks with internal resistors and external capacitors. This provides a frequency response with the tolerances given in Fig.4. A source selector, controlled via the control input ports allows selection of the different modes of operation in accordance with the transmitted signal. The device was designed for a nominal input signal (FM: 54% modulation is equivalent to f = 27 kHz) of 250 mV RMS value (Vi1 and Vi2) and for a nominal input signal (AM: m = 0.54) of 500 mV RMS value (Vi1), respectively 250 mV RMS (Vi3 and Vi4). A nominal gain of 6 dB for Vi1 and Vi2 signals (0 dB for Vi1 signal (AM sound)) and 6 dB for Vi3 and Vi4 signals is built-in. By using rail-to-rail operational amplifiers, the clipping level (THD 1.5%) is 1.60 V RMS for VP = 5 V and 2.65 V RMS for VP = 8 V at outputs Vo1 to Vo3 and Vo4. Care has been taken to minimize switching plops. Also total harmonic distortion and random noise are considerably reduced. Identification The pilot signal is fed via an external RC high-pass filter and single tuned LC band-pass filter to the input of a gain controlled amplifier. The external LC band-pass filter in combination with the external RC high-pass filter should have a loaded Q-factor of approximately 40 to 50 to ensure the highest identification sensitivity. By using a fixed coil (5%) to save the alignment (see Fig.2), a Q-factor of approximately 12 is proposed. This may cause a loss in sensitivity of approximately 2 to 3 dB. A digital PLL circuit generates a reference carrier, which is synchronized with the pilot carrier. This reference carrier and the gain controlled pilot signal are fed to the AM-synchronous demodulator. The demodulator detects the identification signal, which is fed through a low-pass filter with external capacitor CLP (pin 5) to a Schmitt trigger for pulse shaping and suppression of LOW level spurious signal components. This is a measure against mis-identification. The identification signal is amplified and fed through an AGC low-pass filter with external capacitor CAGC (pin 4)
TDA9847
to obtain the AGC voltage for controlling the gain of the pilot signal amplifier. The identification stages consist of two digital PLL circuits with digital synchronous demodulation and digital integrators to generate the stereo or dual sound identification bits which can be indicated via LEDs. A 10 MHz crystal oscillator provides the reference clock frequency. The corresponding detection bandwidth is larger than 50 Hz for the pilot carrier signal, so that fp-variations from the transmitter can be tracked in the event of missing synchronization with the horizontal frequency fH. However the detection bandwidth for the identification signal is made small (1 Hz) to reduce mis-identification. Figure 2 shows an example of the alignment-free fp band-pass filter. To achieve the required QL of around 12, the Q0 at fp of the coil was chosen to be around 25 (effective Q0 including PCB influence). Using coils with other Q0, the RC-network (RFP and CFP) has to be adapted accordingly. It is assumed that the loss factor tan of the resonance capacitor is 0.01 at fp. Copper areas under the coil might influence the loaded Q and have to be taken into account. Care has also to be taken in environments with strong magnetic fields when using coils without magnetic shielding. Control input ports The complete IC is controlled by the four control input ports C1, C2, C3 and C4. Which AF output channel pair can be selected is determined by the control input Port C4 [LOW: main; HIGH: SCART; 3-state: preset position (see Section "General information")]. With the other control input ports C1, C2 and C3 the user can select between different AF sources in accordance with the transmitter status (see Tables 1 and 2). Finally, Schmitt triggers are added in the input Port interfaces to suppress spikes on the control lines C1, C2, C3 and C4. After a Power-On Reset (POR) both registers are reset (mute mode for both AF channel pairs). After some time (1 ms), when the POR is automatically deactivated, the switch positions of the main channel (C4 = LOW) are changed in accordance with the other control input Port levels. If C4 is HIGH after a POR, the switch positions of the SCART channel cannot change. The reason is, that the main register is reset (mute mode; see Table 1). Thus, at first the main register byte has to be changed out of the mute function, e.g. sound mute.
1995 May 23
6
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
After that, when C4 is HIGH (see Table 2), the switch positions of the SCART channel are changed in accordance with the other control line levels. When the supply voltage of the TDA9847 is not connected (standby function), the control lines remain undisturbed. The logic level combination 1000 of the control input ports (C4, C3, C2 and C1) is not allowed (see Tables 1 and 2). Operating mode selection Tables 1 and 2 show the different operating modes of this stereo decoder. MUTE MODE This IC has two different mute modes: 1. Mute mode. 2. Sound mute mode. In the mute mode, when all control input lines are set LOW, all AF channels are muted (`fast mute'). Finally, the integrators are reset provided the user does not leave this mode (identification is disabled). When the user changes this mode, the identification circuit starts with the detection. In the sound mute mode each AF channel can be separately muted (0100 = main and 1100 = SCART). The identification circuit is activated and the LEDs are on or off in accordance with the detection status of this circuit. MONO MODE For the transmitter status mono the user must set the TDA9847 in the mono mode with X001 or X010 (see Tables 1 and 2). The level combination X011 is reserved for the AM sound (standard L), because in this mode the de-emphasis is deactivated and the gain of the AF signal from input to output is reduced from 6 dB to 0 dB. At the AF outputs the signal has the same level for standards with FM or AM modulated sound assuming the same modulation degree. STEREO MODE In this mode the choice between stereo and mono (`forced mono') signals is common for both AF channel pairs. The mode for main and SCART is achieved by control of the main channel (see Tables 1 and 2). DUAL MODE In this mode there is no restriction to select AF inputs and outputs independently in both channels. 1995 May 23 7 EXTERNAL MODE
TDA9847
External sound sources, e.g. from SCART input, are fed to both AF channel pair outputs. When the user chooses the external mode of the main channel (see Table 1), the identification circuit is still running, but the LEDs are switched-off. Programming of the main and SCART register GENERAL INFORMATION The switch positions of both AF channels are directly controlled by the data of the main and SCART register. These registers are programmable by a microcontroller. In the 3-state mode the logic content of the C1, C2 and C3 control lines remains stored in the registers for main and SCART, so the switch positions in the source selector do not change. The logic content of these control lines can be changed without changing the switch positions of the source selector (preset position) to prepare the new operating mode selection for the main or SCART channel. The execution of this new mode is achieved by leaving the preset position (3-state): When the C4 level goes LOW, the logic content of the control lines C1, C2 and C3 are valid for the main channel (see Table 1) and in the event of HIGH the C1, C2 and C3 are valid for the SCART channel (see Table 2). The identification bits and the control lines influence the operating mode selection for the AF switches in the source selector and de-matrix, e.g. both AF channels are programmed in the mono mode (X001, see Tables 1 and 2). The LEDs are switched-off. When the identification circuit detects the stereo identification frequency (fs = 117 Hz) the de-matrix is immediately switched in the stereo mode without changing the control line levels. The stereo signals are routed to all AF outputs. In the event of dual frequency detection (fD = 274 Hz) both dual sounds are fed to the AF output pairs. MICROCONTROLLER WITH 3-STATE OUTPUT PORTS Figure 10 shows an example of an application circuit for TDA9847 (VP = 4.5 to 8.8 V) in conjunction with a microcontroller, which has a LOW/high-ohmic/HIGH output port to control the main and SCART channel (C4 control line). For the C1, C2 and C3 line the microcontroller requires only LOW/HIGH output ports. Two resistors RC4A and RC4B are necessary for the C4 line to generate the 3-state voltage. The values and tolerances of these components are given in Fig.10.
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
When the microcontroller has only open drain ports available for the C1, C2 and C3 control line, external pull-up resistors must be connected to these control lines. Figure 7 shows an example of a timing diagram to program the main and SCART register of the TDA9847 with a microcontroller via the control lines C1, C2, C3 and C4. Both registers are programmed with the same control line levels: C1 = LOW, C2 = HIGH and C3 = LOW. The dual identification frequency is detected and the dual LED is switched-on. The A-signal (dual mode) is fed to all AF outputs (see Tables 1 and 2). This is shown in the beginning of this timing diagram. The second period of time shows the programming of the external mode (C3 goes to HIGH: CC-signal) for the main channel. The switch positions are immediately changed to the external AF source, because the C4 level is LOW. The dual LED is switched-off by the logic (see Section "External mode"). The next periods of time show the way to change the switch positions for the SCART channel to route B-signals to the AF outputs (dual mode: BB). At first the control output Port of the microcontroller for the C4 line goes into the high ohmic state. The changing of the C1, C2 or C3 level has no influence on the register data. In the timing diagram the C1 level changes from LOW-to-HIGH and the C3 level goes from HIGH-to-LOW. In the next steps the C4 line goes from 3-state-to-HIGH, and the level of the other control lines are valid for the SCART channel, and the B-signals are fed (dual mode: BB) to the AF outputs of the main channel. After some time in this example the C1 and C2 levels change from HIGH-to-LOW and the C3 level goes from LOW-to-HIGH (sound mute). The SCART channel is immediately muted, because the level of the C4 line is HIGH. The last period of time shows the programming of the dual mode (AA) for the main channel. At first the control output Port of the microcontroller for the C4 line goes into the high ohmic state. The changing of the C1, C2 or C3 level has no influence on the register data. The switch positions of the SCART channel stay in the sound mute. In the 3-state mode the C2 level changes from LOW-to-HIGH, and the C3 level goes from HIGH-to-LOW. When the C4 level is LOW, the level of the other control lines are valid for the main channel. The A-signal (dual mode) is fed to the main outputs. The operation mode mute (see Table 1) can be achieved from any position of the C4 control line without going via 3-state. 1995 May 23 8
TDA9847
Figure 5 shows the hold and set-up time of the C1, C2 and C3 control line in the 3-state mode, see Chapter "Characteristics". MICROCONTROLLER WITH LOW/HIGH OUTPUT PORTS Figure 11 shows an example of an application circuit for TDA9847 (VP = 4.5 to 8.8 V) in conjunction with a microcontroller, which has open drain output ports to control the main and SCART channel. Four resistors and two output ports of the microcontroller are necessary to generate the 3-state voltage. The other control lines have a pull-up resistor (10 k) in the event of open drain output stages. These resistors are not necessary for LOW/HIGH output ports of the microcontroller having internal pull-up or push-pull stages. The values and tolerances of these components are given in this figure. Table 4 shows the conversion logic truth table. For information about programming the different operation mode selections see Section "Operating mode selection". Power supply The different supply voltages and currents required for the analog and digital circuits are derived from an internal band-gap reference circuit. The AF reference voltage is 1 V . For a fast setting to 1 V an internal start-up circuit 2P 2P is added. A good ripple rejection is achieved with the external capacitor Cref = 100 F/16 V in conjunction with the high ohmic input of the 12VP pin (pin 8). No additional DC load on this pin is allowed. Power-On Reset (POR) When a POR is activated by switching on the supply voltage or because of a supply voltage breakdown, the 117/274 Hz DPLL, the 117/274 Hz integrator and the logic will be reset. Both AF channels (main and SCART) are muted (1 ms). ESD protection All pins are ESD protected. The protection circuits represent the latest state of the art. Internal circuit The internal pin configuration is given in Fig.7.
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Vi Vi Vi Tstg Tamb Ves Note 1. Charge device model class B: discharging a 200 pF capacitor through a 0 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a SDIP24 SO24 PARAMETER thermal resistance from junction to ambient in free air 69 95 VALUE PARAMETER supply voltage (pin 22) input voltage at pins 1 to 3 and 24 input voltage at pins 4 to 17, 21 and 23 input voltage at pins 18 and 19 storage temperature operating ambient temperature electrostatic handling for all pins note 1 CONDITIONS MIN. -0.3 -0.3 -0.3 -0.3 -25 0 -
TDA9847
MAX. +10 +9.0 VP +10 +150 +70 300 V V V V C C V
UNIT
UNIT K/W K/W
CHARACTERISTICS VP = 5 V; Tamb = 25 C; nominal input signal Vi1, 2 = 0.25 V RMS value (FM: 54% modulation is equivalent to f = 27 kHz); nominal input signal Vi1 = 0.5 V RMS value (AM: m = 0.54); nominal input signal Vi3, 4 = 0.25 V RMS value (AM: m = 0.54); nominal output signal Vo1, 2, 3, 4 = 0.5 V RMS value; fAF = 1 kHz; Vi pil = 16 mV RMS value; fpil = 54.6875 kHz (identification frequencies: stereo = 117.48 Hz, dual = 274.12 Hz), 50 s pre-emphasis; noise measurement in accordance with "CCIR468-3", operating oscillator frequency fosc = 10.008 MHz; currents into the IC positive; measured in test circuit Fig.8; unless otherwise specified. SYMBOL Supply VP IP Ptot Vn(DC) Vref(DC) lL(DC) supply voltage (pin 22) supply current (pin 22) total power dissipation DC voltage (pins 9 to 17 and 21) DC reference voltage (pin 8) DC leakage current (pin 8) without LED current 4.5 14 63
1 1 2VP - 0.1 2VP
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
5 15 75
1 1 2VP 2VP
8.8 20 176
1 1 2VP + 0.1 2VP
V mA mW V V A
- 0.1
+ 0.1
-
-
1
1995 May 23
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Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9847
MAX.
UNIT
AF Inputs (Vi1 and Vi2 [pins 9 and 10)] Vi(rms) nominal input signal voltage (RMS value) 54% modulation B/G L (only Vi1) Vi(rms) clipping voltage level (RMS value) THD 1.5% VP = 5 V; B/G VP = 8 V; B/G 0.625 1.050 0.715 1.200 1.400 2.350 6 0 50 5.0 - - - - 7 +1 60 5.75 V V V V dB dB k k - - 0.25 0.5 - - V V
VP = 5 V; L (only Vi1) 1.200 VP = 8 V; L (only Vi1) 2.100 Gv AF signal voltage gain G = Vo/Vi; note 1 B/G L (only Vi1) Ri Rdeem input resistance internal de-emphasis resistor (pins 17 and 21) see Fig.4 5 -1 40 4.25
Additional AF inputs (pins 11 and 12) Vi(rms) Vi(rms) nominal input signal voltage (RMS value) clipping voltage level (RMS value) 54% modulation THD 1.5% VP = 5 V VP = 8 V Gv Ri Vo(rms) Vo(rms) AF signal voltage gain input resistance THD 0.3%; 54% modulation THD 1.5% VP = 5 V VP = 8 V Ro CL RL B B-3 dB THD S/N(W) output resistance load capacitor on output load resistor on output (AC-coupled) frequency response (bandwidth) frequency response total harmonic distortion weighted signal-to-noise ratio fi = 40 to 20000 Hz; note 2 -3 dB; note 2 note 1 1.4 2.4 250 - 10 -0.5 300 - 66 1.6 2.65 350 - - - 350 0.2 75 - - 450 1.5 +0.5 400 0.3 - V V nF k dB kHz % dB G = Vo/Vi; note 1 0.625 1.050 5 40 - 0.715 1.200 6 50 7 60 - - V V dB k - 0.25 - V
AF outputs (pins 13 to 16) nominal output signal voltage (RMS value) clipping voltage level (RMS value) 0.5 V
"CCIR468-3" (quasi-peak)
1995 May 23
10
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
SYMBOL cr dual stereo mute VDC mute attenuation change of DC level output voltage between any two modes of operation power supply ripple rejection DC output current PARAMETER crosstalk attenuation for CONDITIONS notes 1 and 3 Zs 1 k Zs 1 k Zs 1 k; note 1 after switching 70 40 76 - 75 45 80 - - - - 10 MIN. TYP.
TDA9847
MAX.
UNIT dB dB dB mV
PSRR IO(DC) fr fosc
fr = 70 Hz; see Fig.9
50 -
65 -
- 20
dB A
10 MHz crystal oscillator (pin 23) series resonant frequency of crystal (fundamental mode) operating oscillator frequency (running in parallel resonance mode) CL = 20 pF over operating temperature range including ageing and influence of drive circuit even at extremely low drive level (<1 pW) over operating temperature range with C0 = 6 pF 9.995 9.988 10.008 10.008 10.021 10.028 MHz MHz
Rxtal
equivalent crystal series resistance
-
60
200
Rn C0 C1 Pxtal Vosc(p-p)
crystal series resistance of unwanted mode crystal parallel capacitance crystal motional capacitance level of drive in operation oscillator operating voltage (peak-to-peak value) with Rr 100
2 x Rr - - - 500
- 6 25 - 550
- 10 50 5 600
pF fF W mV
Pilot processing Vi pil(rms) Ri pil Ci pil m pilot input voltage level at pin 7 unmodulated (RMS value) pilot input resistance pilot input capacitance modulation depth AM 5 500 - 25 - 1000 - 50 100 - 3 75 mV k pF %
1995 May 23
11
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
SYMBOL fpil PARAMETER pilot PLL pull-in frequency range (referenced to fpil = 54.6875 kHz) CONDITIONS fosc = 9.988 MHz lower side upper side fosc = 10.008 MHz lower side upper side fosc = 10.028 MHz lower side upper side tpil fLP R5 V5(rms) QL pilot PLL pull-in time low-pass frequency response low-pass output resistance identification threshold voltage (RMS value) loaded quality factor of resonance circuit loaded quality factor of resonance circuit with fixed coil tacqui AGC AGC acquisition time high sensitivity; see Fig.1 sensitivity loss 2 to 3 dB; see Fig.2 Vi pil(rms) switched from 0 to 100 mV (RMS value) -3 dB -188 411 0 450 18.75 - 40 - - - - 600 25 - - 12 -188 411 1.7 750 -296 302 - - -296 302 -405 192 - - -405 192 MIN. TYP.
TDA9847
MAX.
UNIT Hz Hz Hz Hz Hz Hz ms Hz k mV
31.25 70 50 -
-
-
0.1
s
Identification (internal functions) Vi tuner C/N H fdet identification voltage sensitivity note 4 pilot carrier-to-noise ratio for start of identification hysteresis pull-in frequency range of identification PLL (referred to fdet stereo = 117.48 Hz and fdet dual = 274.12 Hz) note 5 note 4 lower side stereo dual upper side stereo dual tdet pull-in time of identification PLL (referenced to fdet stereo = 117.48 Hz and fdet dual = 274.12 Hz) identification window frequency width (referred to fdet stereo = 117.48 Hz and fdet dual = 274.12 Hz) integrator time constant stereo dual 0.63 0.69 0 0 - - - - - - - 0.63 0.69 0.8 0.8 Hz Hz s s -0.63 -0.69 - - -0.63 -0.69 Hz Hz - - - 28 33 - - 2 dBV dB/Hz dB
fident
stereo; note 6 dual; note 6
2.2 2.3
2.2 2.3
Hz Hz
tintegr
0.94
0.94
s
1995 May 23
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Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
SYMBOL tident(on) tident(off) PARAMETER total identification time on total identification time off CONDITIONS stereo; note 7 dual; note 7 stereo; note 8 dual; note 8 LED (pins 18 and 19) VL(off) VL(on) IL(off) IL(on) output voltage output voltage input current input current LED off LED on LED off LED on - - - - - - - - - 5.0 - - - 1.8 5.0 - - - - - - - 8.8 0.7 1 12 MIN. 0.35 0.35 0.60 0.60 - - - - TYP.
TDA9847
MAX. 2.0 2.0 1.5 1.5 s s s s
UNIT
V V A mA
Control input ports C1 to C3 (pins 1, 2 and 24) VIL VIH IIL IIH VIL VCT VIH IIL ICT IIH th1 th2 tsu1 tsu2 LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current 0 2.0 - - 0.8 8.8 -1 1 V V A A
Control input Port C4 (pin 3) LOW level input voltage 3-state level input voltage HIGH level input voltage LOW level input current 3-state level input current HIGH level input current HIGH level hold time LOW level hold time HIGH level set-up time LOW level set-up time see Fig.5 see Fig.5 see Fig.5 see Fig.5 0 1.5 2.8 - - - 5 5 0.25 0.25 0.8 2.1 8.8 -1 -1 1 - - - - V V V A A A s s s s
Notes to the characteristics 1. Vo = 0.5 V (RMS value); f = 1 kHz. 2. Without de-emphasis capacitors with respect to nominal gain. 3. In dual mode: A (B)-signal into B (A) channel; in stereo mode: R-signal into left channel; L-signal = 0. 4. Tuner input signal, measured with PCALH reference front end (12EMF, 75 , 2T/20T/white bar, 100% video) and PC/SC1 = 13 dB; PC/SC2 = 20 dB. The pilot band-pass has to be aligned. 5. Bandwidth of the pilot BP-filter B-3 dB = 1.2 kHz. Vi2 input driven with identification-modulated pilot carrier and white noise. 6. Identification window is defined as twice the pull-in frequency range (lower plus upper side) of identification PLL (steady detection) plus window increase due to integrator (fluctuating detection). 7. The maximal total system identification time on is equal to tident(on) plus tacqui AGC. 8. The maximal total system identification time off is equal to tident(off).
1995 May 23
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Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
Table 1 Control input Port matrix to select AF inputs and AF outputs (main channel) INPUT SIGNAL MODE ST/DS/M Vi1 9 Mute(2) Sound mute Mono - - M - - M M AM Stereo ST S S S Dual DS A A A External - - - - Notes 1. The combination 1000 is not allowed. Vi2 10 - - - - - R R R B B B - - - SCART Vi3 11 - - - - - - - - - - - C C C Vi4 12 - - - - - - - - - - - D D D OUTPUT SIGNAL MAIN Vo1 14 Vo2 13 SCART Vo3 16 Vo4 15 CONTROL INPUT PORT(1) C4 3 0 0 0 0 0 L S S R S S 0 0 0 0 0 0 note 3 0 0 0 C3 24 0 1 0 0 0 0 0 0 0 0 0 1 1 1 C2 2 0 0 0 1 1 0 1 1 0 1 1 0 1 1 C1 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1
TDA9847
LED DUAL 18 off off off off off off off on on on off off off STEREO 19 off off off off on on on off off off off off off
no signal no signal M M AM L S S A A B C C D M M AM R S S B A B D C D
no signal note 3 note 3
note 4 note 4
note 3
2. In mute mode the content of the 117 Hz/274 Hz integrator will be reset. The LEDs are switched-off. 3. The previous state is unchanged. 4. The LED shows the identification status.
1995 May 23
14
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
Table 2 Control input Port matrix to select AF inputs and AF outputs (SCART channel) INPUT SIGNAL MODE ST/DS/M Vi1 9 Sound mute Mono - M - M M AM Stereo ST S S S Dual DS A A A External - - - - Notes 1. The combination 1000 is not allowed. 2. The previous state is unchanged. Table 3 Explanation of Tables 1 and 2 DESCRIPTION right left ( L + R) -------------------2 dual sound A/B external sound source (SCART) AM sound (standard L) mono sound dual sound stereo sound Table 4 Vi2 10 - - - - R R R B B B - - - SCART Vi3 11 - - - - - - - - - - C C C Vi4 12 - - - - - - - - - - D D D note 2 note 2 note 2 OUTPUT SIGNAL MAIN Vo1 14 Vo2 13 SCART Vo3 16 M M AM - - - A A B C C D Vo4 15 M M AM - - - B A B D C D C4 3 1 1 1 1 1 1 1 1 1 1 1 1 1
TDA9847
CONTROL INPUT PORT(1) C3 24 1 0 0 0 0 0 0 0 0 0 1 1 1 C2 2 0 0 1 1 0 1 1 0 1 1 0 1 1 C1 1 0 1 0 1 1 0 1 1 0 1 1 0 1
note 2 note 2
no signal
SIGNAL R L S A and B C and D AM M DS ST
Conversion logic truth table for the C4 control line (see Fig.11) TDA9847 C4 1 3-state 0 not allowed C4-level 3.2 V 1.8 0.25 V 0.45 V undefined
MICROPROCESSOR OUTPUT CONTROL PORTS C41 0 1 1 0 C42 0 0 1 1
1995 May 23
15
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
TDA9847
+2 VoAF (dB) +1 R: -15%; C: -5%
MED647
0
-1
R: +15%; C: +5%
-2 10
10 2
10 3
10 4
foAF (Hz)
10 5
Fig.4
Tolerance scheme of AF frequency response; de-emphasis with CD1, CD2 = 10 nF (5%); Rinternal = 5 k (15%).
V C4 (V) HIGH
2.8
5
3-state
2.1 1.5 0.8
LOW 0 VC1/C2/C3 (V) 5 HIGH t h1 t h2 t su1 t su2 t h1 t h2 t su1 t su2
t (s)
2
0.8
LOW 0
t (s)
MED811
Fig.5 Waveforms showing the hold and set-up times of the C1 to C3 control line in the 3-state mode.
1995 May 23
16
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
TDA9847
V C1 (V) HIGH 5
2
0.8
LOW 0
t (s)
V C2 (V) HIGH 5
2
0.8
LOW 0
t (s)
V C3 (V) 5 HIGH
2
0.8
LOW 0
t (s)
V C4 (V) 5 HIGH
2.8
3-state
2.1 1.5 0.8 t (s)
LOW 0 valid main AF outputs main SCART dual: AA dual: AA external: CC dual: BB sound mute
MED810
storage main
valid SCART
storage SCART
valid main dual: AA
Fig.6
Programming the main and SCART register of the TDA9847 with a microcontroller via the control lines C1 to C4; the dual identification frequency is detected.
1995 May 23
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Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
INTERNAL CIRCUITRY
TDA9847
VP 3 A 1 2 k 5 k
VP 3 A 2 k 24 23
C1
C3 XTAL
VP 3 A 2 2 k
- + +5 V
22
C2
VP
13 k VP 3 A VP 3 A
3 pF
C4
3
2 k
CAGC
4
25 k
60 A VP VP 19 LEDST
VP CLP 5 25 k
40 A
VP
VP 60 A 18 LEDDU
Z\xV
CDCL 6
P
VP 40 A
25 k
Vi pil
C ref
8 22.5 k 5 k 9 VP 5 k
IB
Vi1
15 k
IB
35 k Vi2 10 50 k
IB
Z\xV
P
AF outputs IB AF inputs
Z\xV
Vi3 11 50 k
P
200 A VP
IB
Z\xV
Vi4 12 50 k
P
IB
Z\xV
P
VP
MED807
ESD protection diode for pins 4 to 17, 21 and 23
zener diode protection for pins 1, 2, 3, 18, 19, 20 and 24
Fig.7 Internal circuits.
1995 May 23
18
-
7
+
5 k
5 k
- - + 20 5 k 17 - + VP 16 200 A VP 15 VP 200 A 14 13 200 A
+
TDA9847
5 k
21
C
D2
GND
C
D1
Vo3
Vo4
Vo1
Vo2
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
TEST AND APPLICATION INFORMATION
TDA9847
C1 control input ports
1
24
XTAL CVP
C3 control input port 10 MHz
C2
2
23
VP 10 F 50 s de-emphasis
C4 CAGC CLP CDCL 10 F
3
22
100 F/16V Cref
4 10 nF
5% 21 CD2 10 nF 20
5
1/2 VP
100 nF
6
19
stereo transmission 1 k VP
TDA9847
3.3 nF 2.5 mH 7 18 5% CD1 10 nF Vo3
47 pF 8 30 k AF from 5.5 MHz V or from AM demodulator (L) i1 AF from 5.742 MHz Vi2 external sound V i3 source C SCART external sound V i4 source D 12 4 x 2.2 F 13
MED806
dual transmission 50 s de-emphasis
17
2.2 k 9 2.2 k 16
SCART 10 15 Vo4 Vo1 main Vo2
11
14
Fig.8 Test circuit of the stereo decoder TDA9847.
1995 May 23
19
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
TDA9847
20 VP 16 22 15
TDA9847
10 k 100 F 5 V modulated with 200 mV (p-p) 8 9 10 11 12 100 F 14 13
HP3585
70 Hz
100 F/16V
MED808
Fig.9 Test circuit for measurement of ripple rejection.
VP = 5 V 10% VP = 4.5 to 8.8 V RC4A 11 k
C4
3
22
RC4B 6.2 k STEREO DECODER C1 C2 C3 24 20 1 2
MICROCONTROLLER
TDA9847
MED809
All resistors: 2%.
Fig.10 Application circuit for the stereo decoder TDA9847 in conjunction with a microcontroller [LOW/HIGH output ports with internal pull-ups or push-pull stages (C1 to C3) and LOW/high-ohmic/HIGH output Port (C4)].
1995 May 23
20
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
TDA9847
VP = 5 V 10% RC42A 10 k C41 RC41A 10 k R C41B 100 k C42 MICROCONTROLLER RC1 10 k RC2 10 k RC42B 100 k RC3 10 k
VP = 4.5 to 8.8 V
RC4A 11 k C4 RC4B 6.2 k 3
22
STEREO DECODER
TDA9847
C1 1 C2 2 C3 24
20
MED812
Resistors RC4A and RC4B 2%; all other resistors 10%; transistors BC types or equivalent.
Fig.11 Application circuit for the stereo decoder TDA9847 in conjunction with a microcontroller (LOW/HIGH with open-drain output ports).
1995 May 23
21
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
PACKAGE OUTLINES SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
TDA9847
SOT234-1
D seating plane
ME
A2
A
L
A1 c Z e b 24 13 b1 wM (e 1) MH
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT234-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 22.3 21.4 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
ISSUE DATE 92-11-17 95-02-04
1995 May 23
22
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
TDA9847
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1995 May 23
23
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s. Plastic small outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW
TDA9847
Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
1995 May 23
24
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9847
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1995 May 23
25
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
NOTES
TDA9847
1995 May 23
26
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with digital identification
NOTES
TDA9847
1995 May 23
27
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 15/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)480 6960/480 6009 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD40 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/02/pp28 Document order number: Date of release: 1995 May 23 9397 750 00154

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